1. Field of the Invention
The present invention relates to a method of forming a metal wiring line of a semiconductor device.
2. Description of the Related Art
With the enlargement of a chip size and the miniaturization of a minimum processing dimension, an interval between wiring lines, the sectional area of the wiring line decrease, and the length of the wiring line increases. In association with them, the capacitance and resistance of the wiring line are sharply increased, resulting in a larger propagation delay of a signal.
In order to reduce the wiring line capacitance, it is tried to decrease the dielectric constant of an interlayer insulating film. An insulating material with a small dielectric constant is typically used in order to decrease the dielectric constant to a small value. For example, a method is known of decreasing the relative dielectric constant to about 3 by doping impurities into a conventional inorganic silicon dioxide film with the relative dielectric constant of 4.2. Otherwise, a method is known of using an organic polymer with the relative dielectric constant of 2 to 3, as the insulating film. This dielectric constant value is lower than that of the silicon dioxide film.
As a method of decreasing the wiring line resistance, a method is known of replacing aluminum with the specific resistance of 3.0 Ωcm used in the conventional wiring line by copper with the specific resistance of 1.7 Ωcm. Also, since an average wiring line length is inversely proportional to the number of wiring layers, the wiring line may be formed as a multiple-layer. Also, the multiple-layer wiring line is formed to have a wider width. In this case, of the wiring line, the upper layer having the smaller resistance is used for global wiring, and the lower layer is used for local wiring in a highly integrated circuit. This structure can decrease the wiring line resistance while reducing the chip area. As a result, the employment of those methods makes it the propagation delay to be largely reduced.
However, the conventional multiple-layer wiring technique has the following problems. That is, the problems will be described with reference to FIGS. 1A to 1C. FIGS. 1A to 1C are cross section views showing a process for forming a damascene wiring line in a semiconductor device.
The semiconductor device shown in FIGS. 1A to 1C includes a substrate 101, an interlayer insulating film 102, a hard mask 103, a barrier film 104, a metal wiring line film 105 and a wiring line groove 106.
The substrate 101 is a silicon substrate on which semiconductor elements, wiring lines and the like are formed.
The interlayer insulating film 102 is an insulating film formed of an organic material such as a polymer of a hydrocarbon system. The dielectric constant of the interlayer insulating film 102 is small, differently from an inorganic insulating film such as a silicon dioxide film. For example, the interlayer insulating film 102 has the relative dielectric constant of 2.0 to 3.0.
The hard mask 103 is an insulating film formed of an inorganic material such as silicon dioxide. However, the hard mask 103 may be formed of silicon dioxide including hydrogen group or methyl group such as silicon nitride (SiN), silicon carbide (SiC), silicon carbide nitride (SiCN), MSQ (Methyl Silsesquioxane) and HSQ (Hydrogen Silsesquioxane). The structure of the hard mask is not limited to a single layer. The hard mask 103 may has a lamination structure in which a plurality of films are laminated. The hard mask 103 is essential to protect the interlayer insulating film 102 in a photolithography process for forming a wiring line groove. Also, the hard mask 103 has a stopper function when the barrier film 104 is polished by using a chemical mechanical polishing (CMP) method.
The barrier film 104 is a thin metal film. The barrier film 104 protects the metal wiring line film 105 from being diffused into the interlayer insulating film 102. For example, the barrier film 104 is formed of titanium nitride and tantalum.
The metal wiring line film 105 is formed of a metal with a small specific resistance. The metal wiring line film 105 is formed in the wiring line groove formed in the insulating film, and is used for a damascene wiring line. For example, the metal wiring line film 105 is formed of copper.
Next, the manufacturing process will be described below.
In FIG. 1A, the interlayer insulating film 102 and the hard mask 103 are formed on the substrate 101 in order. Then, wiring line grooves 106 are formed by the photolithography process. After that, the barrier film 104 and the metal wiring line film 105 are deposited.
In FIG. 1B, the metal wiring line film 105 is polished by a first CMP polishing process in which the barrier film 104 is used as a stopper film. Consequently, an upper portion of the metal wiring line film 105 located above the barrier film 104 is removed.
In FIG. 1C, the barrier film 104 is polished by a second CMP polishing process in which the hard mask 103 is used as a stopper film. Consequently, the barrier film 104 and an upper portion of the metal wiring line films 105 located above the hard mask 103 are removed.
However, as shown in FIGS. 1A to 1C on the left sides, in a portion in which the wiring lines are dense, a rate of a total area of the exposed metal wiring line films 105 is equal to or greater than that of the exposed hard mask 103. For this reason, when the barrier film 104 is polished in the second polishing process, the hard mask 103 is excessively polished and thinned around the exposed portion of the metal wiring line films 105. On the other hand, such phenomenon is never caused in the right side portion of FIGS. 1A to 1C. That is, the hard mask 103 remains in its original state. Thus, since the cross section area of the wiring lines are different depending on a position, the pattern dependency of the wiring line resistance becomes larger.
Also, since the polishing result of the hard mask 103 is different depending on the position, many concave and convex portions are induced on the surface of the substrate. When a multiple-layer wiring line is to be formed, concave and convex portions become larger in the upper layer if a step difference due to the concave and convex portions are induced for each layer. In this case, because of a focal depth in an exposing process, it is difficult to form the desirable film pattern. Hence, a CMP-polishing process of the interlayer insulating film is required in order to solve the step difference.
In addition, in the conventional technique, the hard mask 103 remains in its original state even after the CMP polishing process. The hard mask 103 is typically an inorganic insulating film, and the dielectric constant of the hard mask 103 is larger than that of the interlayer insulating film 102. Thus, the wiring line capacitance increases due to the difference in the dielectric constant. The increase in the wiring line capacitance leads to the increase in the propagation delay. Hence, this has a severe influence on the improvement of an integration degree.
In conjunction with the above-mentioned description, Japanese Laid Open Patent Application (JP-A-Heisei 11-274122) discloses a semiconductor device and a method of manufacturing the same. This reference will be described below with reference to FIGS. 1A to 1C. This reference uses an organic SOG film as the hard mask 103. Because the dielectric constant of the organic SOG film is smaller than that of silicon dioxide film, a parasitic capacitance between wiring lines can be reduced. Also, in the CMP polishing process using aluminum abrasive particles, the hard mask 103 functions as an effective stopper in the second CMP polishing process of the barrier film 104 in FIG. 1C. However, the dielectric constant of the organic SOG film is higher than that of the interlayer insulating film 102. Also, the organic SOG film is not removed after the second CMP polishing process.
Also, Japanese Laid Open Patent Application (JP-P2000-223490A) discloses a method of manufacturing a semiconductor device. This reference will be described below with reference to FIGS. 1A to 1C. In this reference, the hard mask 103 is removed by plasma etching after the second CMP polishing process of the barrier film 104 in FIG. 1C. Then, an entire copper wiring is covered by an insulating film with a low dielectric constant formed of the same material as the interlayer insulating film 102. Through the above-mentioned processes, the parasitic capacitance between the wiring lines can be largely reduces. However, the hard mask 103 is removed by a plasma etching, so that a tact time increases extremely, and the throughput decreases extremely. Also, there may be a possibility of increase in a cost of a processing apparatus.